| Value |
Bit Setting |
Meaning |
| 0x00000001 |
IE |
Interrupt enable |
| 0x00000002 |
EXL |
Exception level |
| 0x00000004 |
ERL |
Error level |
| 0x00000008 |
S |
Supervisor mode |
| 0x00000010 |
U |
User mode |
| 0x00000018 |
U |
Undefined (implemented as User mode) |
| 0x00000000 |
K |
Kernel mode |
| 0x00000020 |
UX |
User mode 64-bit addressing |
| 0x00000040 |
SX |
Supervisor mode 64-bit addressing |
| 0x00000080 |
KX |
Kernel mode 64-bit addressing |
| 0x0000FF00 |
IM=i |
Interrupt Mask value is i |
| 0x00010000 |
DE |
Disable cache parity/ECC |
| 0x00020000 |
CE |
Reserved |
| 0x00040000 |
CH |
Cache hit |
| 0x00080000 |
NMI |
Non-maskable interrupt has occurred |
| 0x00100000 |
SR |
Soft reset or NMI exception |
| 0x00200000 |
TS |
TLB shutdown has occurred |
| 0x00400000 |
BEV |
Bootstrap vectors |
| 0x02000000 |
RE |
Reverse-Endian bit |
| 0x04000000 |
FR |
Additional floating-point registers enabled |
| 0x08000000 |
RP |
Reduced power mode |
| 0x10000000 |
CU0 |
Coprocessor 0 usable |
| 0x20000000 |
CU1 |
Coprocessor 1 usable |
| 0x40000000 |
CU2 |
Coprocessor 2 usable |
| 0x80000000 |
XX |
MIPS IV instructions usable |
