PA-RISC Floating-Point Registers

The PA-RISC has 32 floating-point registers. The first four are used for status and exception registers. The rest can be addressed as 64-bit doubles, as two 32-bit floats in the right and left sides of the register, or even-odd pairs of registers as 128-bit extended floats.

Register
Description
Data Type
Edit
Dive
Specify in Expression
status
Status register
<int>
no
no
$status
er1-er7
Exception registers
<int>
no
no
$er1-$er7
fr4-fr31
Double floating-point registers
<double>
yes
yes
$fr4-$fr31
fr4l-fr31l
Left half floating-point registers
<float>
yes
yes
$fr4l-$fr31l
fr4r-fr31r
Right half floating-point registers
<float>
yes
yes
$fr4r-$fr31r
fr4/fr5-fr30/fr31
Extended floating-point register pairs
<extended>
yes
yes
$fr4_fr5-$fr30_fr31

The floating-point status word controls the arithmetic rounding mode, enables user-level traps, enables floating-point exceptions, and indicates the results of comparisons.

Type
Value
Meaning
Rounding Mode
0
Round to nearest

1
Round toward zero

2
Round toward +infinity

3
Round toward -infinity
Exception Enable and Exception Flag Bits
V
Invalid operation
Z
Division by zero

O
Overflow

U
Underflow

I
Inexact result
Comparison Fields
C
Compare bit; contains the result of the most recent queued compare instruction.

CQ
Compare queue; contains the result of the second-most recent queued compare through the twelfth-most recent queued compare. Each queued compare instruction shifts the CQ field right one bit and copies the C bit into the left-most position.
This field occupies the same bits as the CA field and is undefined after a targeted compare.

CA
Compare array; an array of seven compare bits, each of which contains the result of the most recent compare instruction targeting that bit.
This field occupies the same bits as the CQ field and is undefined after a queued compare.
Other Flags:
T
Delayed trap

D
Denormalized as zero

 
 
 
 
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