MIPS FCSR Register

For your convenience, TotalView interprets the bit settings of the MIPS FCSR register. You can edit the value of the FCSR and set it to any of the bit settings outlined in the following table.

Value
Bit Setting
Meaning
RM=RN
0x00000000
Round to nearest
RM=RZ
0x00000001
Round toward zero
RM=RP
0x00000002
Round toward positive infinity
RM=RM
0x00000003
Round toward negative infinity
flags=(I)
0x00000004
Flag=inexact result
flags=(U)
0x00000008
Flag=underflow
flags=(O)
0x00000010
Flag=overflow
flags=(Z)
0x00000020
Flag=divide by zero
flags=(V)
0x00000040
Flag=invalid operation
enables=(I)
0x00000080
Enables=inexact result
enables=(U)
0x00000100
Enables=underflow
enables=(O)
0x00000200
Enables=overflow
enables=(Z)
0x00000400
Enables=divide by zero
enables=(V)
0x00000800
Enables=invalid operation
cause=(I)
0x00001000
Cause=inexact result
cause=(U)
0x00002000
Cause=underflow
cause=(O)
0x00004000
Cause=overflow
cause=(Z)
0x00008000
Cause=divide by zero
cause=(V)
0x00010000
Cause=invalid operation
cause=(E)
0x00020000
Cause=unimplemented
FCC=(0/c)
0x00800000
FCC=Floating-Point Condition Code 0; c=Condition bit
FS
0x01000000
Flush to zero
FCC=(1)
0x02000000
FCC=Floating-Point Condition Code 1
FCC=(2)
0x04000000
FCC=Floating-Point Condition Code 2
FCC=(3)
0x08000000
FCC=Floating-Point Condition Code 3
FCC=(4)
0x10000000
FCC=Floating-Point Condition Code 4
FCC=(5)
0x20000000
FCC=Floating-Point Condition Code 5
FCC=(6)
0x40000000
FCC=Floating-Point Condition Code 6
FCC=(7)
0x80000000
FCC=Floating-Point Condition Code 7

 
 
 
 
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