Using the MIPS FCSR Register

You can change the value of the MIPS FCSR register within TotalView to customize the exception handling for your program.

For example, if your program inadvertently divides by zero, you can edit the bit setting of the FCSR register in the Stack Frame Pane. In this case, you would change the bit setting for the FCSR to include 0x400. The string displayed next to the FCSR register should now include enables=(Z). Now, when your program divides by zero, it receives a SIGFPE signal, which you can catch with TotalView. See Setting Up a Debugging Session and Handling Signals for more information.